The present invention is related to dynamic random access memories (DRAMs) and more specifically to a system and method of amplifying a signal, e.g. a bitline signal, by a transistor of a DRAM array.
As the storage capacity of an integrated circuit (IC) memory is increased from one generation to the next, the sizes of memory arrays increase, as measured in terms of the row and column space of the array, i.e., the number of wordlines of the memory array, as multiplied by the number of bitlines of the memory array. Memory arrays having larger numbers of wordlines and bitlines generally have less overhead in form of support circuitry for accessing the arrays, as a percentage of the total IC area occupied by the memory. Support circuitry including row decoders, wordline drivers, column decoders, first sense amplifiers and second sense amplifiers, etc. must be provided for every memory array on the IC. However, such support circuitry takes up a significant amount of IC area that cannot be used for the storage of data. To increase the utilization efficiency of IC area, it is therefore advantageous to increase the numbers of wordlines and bitlines of each memory array relative to the numbers of circuits provided therein for support of the memory array.
In a conventional dynamic random access memory (DRAM), it is evident that a single memory array cannot have a row space including an arbitrary or unlimited number of wordlines that is served by a single set of the same bitlines, because the bitlines which span the row space would have very large capacitance. This bitline capacitance, in turn, would make the charge stored on a capacitor of a storage cell coupled to the bitline appear as an extremely small signal, making it difficult to read the storage cell. In addition, very large capacitance of the bitline would have an RC time constant which inhibits the speed of accessing cells of the memory array. Even at the scale of integration density in today's leading DRAM technology, bitline capacitance can be, for example, 200 fF, which significantly exceeds the capacitance of a storage cell within the DRAM, being, for example, 30 fF, such that bitline capacitance may soon become a limiting factor in the design of DRAMs. Thus, in currently available DRAM technology, the number of wordlines in a memory array is limited by the maximum tolerable bitline capacitance. Since the bitline capacitance is directly related to the number of wordlines in a memory array that the bitline spans, bitline capacitance has heretofore limited the size of a memory array, and has hindered the more efficient use of memory chip area, and the ratio of area used for the area memory array to the area used for support circuiting is not improving as fast as would be desired.
It would be desirable, therefore, to be able to extend bitlines of a memory array to much greater lengths than heretofore possible without causing tolerances for the bitline capacitance to be exceeded, and without significantly increasing the area required for support circuitry outside the memory array. In such way, the utilization rate of chip area for the memory array versus support circuitry can be improved.
FIG. 1A illustrates schematically, in plan view, a memory cell array of a dynamic random access memory (DRAM). As shown in FIG. 1A, a memory cell array 10 of a DRAM includes a plurality of storage cells 12, each including a capacitor 11 as a storage element and an access transistor 13 for controlling the storing and reading of a data bit to and from the capacitor 11 of the storage cell 12. A plurality of substantially parallel wordlines 14 and 15 are provided for operating the access transistors 13. A plurality of substantially parallel bitlines 16 and 17 are also provided, each coupled to storage cells 12 of the array 10 and a sense amplifier 18 for transferring a data bit signal therebetween.
In a typical read operation, a wordline 14 is activated by raising the voltage thereon to turn on transistors 13 that have gates coupled to the wordline 14, such that charge stored on capacitors 11 of storage cells 12 connected to those transistors 13 is transferred to corresponding ones of the bitlines 16. On each bitline 16, therefore, a data bit signal corresponding to one accessed storage cell is transferred to a corresponding sense amplifier 18. The sense amplifier 18 amplifies a small voltage difference signal between the bitline 16 that is currently accessed and a non-accessed bitline 17 to full high and low logic levels, thereby determining the value of the data bit read from the storage cell 12. Writeback is then usually performed from the sense amplifier 18 to the storage cell 12, because the charge stored prior thereto on the storage capacitor 11 is transferred to the bitline 16 when the data bit signal is read, and therefore no longer exists in storage capacitor 11. When a wordline 14 is activated, a bitline 16 is accessed, while bitline 17 acts only as a reference input to sense amplifier 18, such that noise that may be present on both the bitline 16 and the reference bitline 17 cancel each other out in sense amplifier 18. On the other hand, when a different wordline 15 is activated, a storage cell 12 on a bitline 17 is accessed, while bitline 16 acts only as a reference input to a corresponding sense amplifier. When both bitline 16 and reference bitline 17 are located adjacent to each other in the same array, as described here, this is known as folded bitline sensing.
A typical write operation begins by first reading the storage cell 12 that is to be written. This is performed by activating a wordline 14, which turns on all of the transistors 13 of storage cells 12 coupled to the wordline 14. This has the effect of clearing the data bit stored before that time from the storage cell 12 because the charge stored before that time in capacitors 11 of storage cells 12 coupled to that wordline 14 are transferred to corresponding bitlines 16. Signals representing data bits stored in each of the storage cells 12 coupled to the wordline 14 are then transferred on respective bitlines 16 to sense amplifiers 18 where the signals are then amplified to high and low logic levels. Thereafter, data bit signals are written to a selected set of the storage cells 12 that are accessed by the active wordline 14, while the remaining storage cells 12 accessed by the activated wordline 14 are written back from sense amplifiers 18, i.e. rewritten with the data that they stored prior to being read.
FIG. 1B schematically illustrates the configuration of a storage cell 12 of a memory array 10, in relation to which embodiments of the invention are provided. The storage cell 12 comprises a storage capacitor 22 having one plate tied to a fixed potential (typically ground as shown in FIG. 1B or in some implementations, half of the bitline high voltage) and having its other plate tied to the sources of access transistors 24. The access transistors 24 are coupled in parallel, having drains tied to bitline 16 and gates tied to wordline 14.
FIG. 1C illustrates an array of storage cells 12, which is described in commonly assigned published U.S. Patent Application No. 2002/0196651 A1 and is background to the present invention, but which is not admitted to be prior art. The illustrated cross section is shown in the direction of a bitline 16. As shown in FIG. 1C, storage capacitor 22 is formed within the deep trench 20 etched into a single crystal semiconductor of a substrate 26. A heavily doped buried strap region 28 is provided along sidewalls of deep trench 20, functioning as the source of an access transistor 24 (hereinafter, the “source”). This buried strap source region 28 is electrically connected to the node electrode 21 formed within the lower region of the deep trench 20, thus forming the connection between access transistor 24 and the storage capacitor 22. A characteristic of the arrangement shown in FIG. 1C is that the access transistors 24 are formed on both sides of deep trench 20, which provides the equivalent of twice the channel width of other transistors having comparable gate lengths. The conduction channels of access transistors 24 are formed along sidewalls of an upper region of the deep trench 20 above the buried strap source regions 28. Additionally, the gates of the access transistors 24 are formed within the upper region of deep trench 20, above the trench top oxide (TTO) 32. The drains are formed in regions on both sides of the trench 20. Deep trench 20 also includes trench collar oxide 30 and trench top oxide 32, which prevent parasitic current leakages.
The gates of access transistor 24 include a deposited doped polysilicon (hereinafter, “poly”) 34 within the upper region of deep trench 20, overlying a gate oxide 36, which is formed on sidewalls in the upper region of the trench 20. As further shown in FIG. 1C, the gate poly 34 is contacted from above by an active wordline 14. Each access transistor 24 further includes a drain region 38 located at or near the top surface of the single-crystal semiconductor of the substrate. Each drain region 38 is connected to the bitline 16 via bitline contacts 23.
Note that other wordlines 15 are shown in FIG. 1C. These wordlines are connected to other storage cells, but not the storage cells being illustrated in FIG. 1C. As such, those wordlines 15 are referred to as passing wordlines as per FIG. 1C, whereas the wordline 14 contacting gate poly 34 is referred to as an active wordline. In an exemplary embodiment, wordlines 14 and 15 include a low resistance conductor layer 42 overlying an optional barrier layer, which in turn, overlies a polysilicon layer 40. For example, a wordline may include a dual layer conductor having a tungsten or tungsten silicide (WSi) layer 42 overlying a barrier layer including tungsten nitride (WN), which in turn, overlies a polysilicon layer 40. The conductive layers 40, 42 of each wordline are surrounded by a nitride insulating layer 44 to insulate the wordlines from bitline contacts 23 and the bitline 16.
The gate poly 34 is insulated from adjacent features, such as doped drain regions 38, by an insulating spacer 46 and insulating trench cap 48. Spacer 46 is preferably formed of an oxide layer and trench cap 48 is preferably formed of a nitride. Other materials could be substituted depending upon the process flow, provided adequate isolation is provided to gate poly 34. The passing wordline 15 is insulated from the doped regions 38 by an array top oxide (ATO) 39.
Referring again to FIG. 1C, note that each storage cell 12 comprises two access transistors 24. Each transistor shares a common gate poly 34, but there are two gate oxides 36, two sources 28, and two drains 38. Each drain region 38 of each transistor has two contacts 23 to the bitline 16. Each transistor 24 further shares a common drain region 38 with a neighboring transistor.
In view of the foregoing, it would be desirable to increase the length of bitlines or permit bitline capacitance to increase, while providing a way for bitline signals to be distinguished, and without having to increase the access time of the memory array.
It would further be desirable to amplify a bitline signal locally, by a transistor of an array of transistors including a storage cell transistor array spanned by the bitline.
It would further be desirable to construct an amplifier including a transistor of an array of transistors including a storage cell array transistor.
It would further be desirable to fabricate the transistor of such amplifier within the same well within which transistors of an array of transistors of a memory are provided.